1. Field of the Invention
The present invention relates to an NTSC digital picture magnifying circuit for outputting video signals of which the number of samples of each of color difference signals is 1/2 or 1/4 of the number of samples of a luminance signal (hereinafter, these video signals are referred to as 4 : 2 : 1 video signal or 4: 1: 1 video signals), in particular, a horizontal magnifying circuit for video signals.
2. Description of the Related Art
FIG. 3A is a block diagram showing a structure of a digital picture magnifying circuit according to a related art reference disclosed as Japanese Patent Laid-Open Publication No. 2-2040. In FIG. 3A, a horizontal compensation memory portion 11 that composes a compensation memory 10 stores horizontal multiplication information X1 of multiplication information X through a CPU bus 4. Likewise, a vertical compensation memory portion 12 that composes the compensation memory 10 stores vertical multiplication information X2 of the multiplication information X through the CPU bus 4. The horizontal compensation memory portion 11 and the vertical compensation memory portion 12 output a horizontal compensation clock signal CX1 and a vertical compensation clock signal CX2, respectively, as a compensation clock signal C.
An address circuit 20 comprises inverters 21 and 22, a horizontal counter 23, a vertical counter 24, and selectors 25 and 26. The inverters 21 and 22 invert the horizontal clock signal C1 and the vertical clock signal C2 of the clock signal C, respectively. The horizontal counter 23 generates a read address A1 corresponding to the horizontal clock signal C1 that is output from the inverter 21. The vertical counter 24 generates a read address A2 corresponding to the vertical clock signal C2 that is output from the inverter 22. The selector 25 outputs as an address AX1 one of a horizontal storage address Ax1 of a storage address AX and a read address A1 to the horizontal compensation memory portion 11. The selector 26 outputs as an address AX2 one of a vertical storage address Ax2 and the read address A2 to the vertical compensation memory portion 12.
A counter circuit 30 comprises inverters IN1 and IN2, AND gates 31 and 32, a horizontal counter 33, a vertical counter 34, a switch S1 and S2, AND gates 35 and 36, and OR gates 37 and 38. The inverters IN1 and IN2 invert the horizontal compensation clock signal CX1 and the vertical compensation clock signal CX2, respectively. The AND gate 31 ANDs the horizontal clock signal C1 and the compensation clock signal CX1 that is output from the inverter IN1. The AND gate 32 ANDs the vertical clock signal C2 and the compensation clock signal CX2 that is output from the inverter IN2. The horizontal counter 33 generates a compensation address AC. A gate output signal D1 of the AND gate 31 is input to a one-bit LSB portion 33L of the horizontal counter 33. Likewise, the vertical counter 33 generates the compensation address AC. A gate output signal D2 of the AND gate 32 is input to a one-bit LSB portion 34L of the vertical counter 34. The switch S1 is opened or closed corresponding to the magnification information X. When the horizontal magnification information X1 represents an enlargement, the switch S1 is opened. When the horizontal magnification information X1 represents a reduction, the switch S1 is closed. Likewise, the switch S2 is opened or closed corresponding to the magnification information X. When the horizontal magnification information X2 represents an enlargement, the switch S2 is opened. When the horizontal magnification information X2 represents a reduction, the switch S2 is closed. The AND gate 35 ANDs the horizontal clock signal C1 and the compensation clock signal CX1 that is output from the switch S1. The AND gate 36 ANDs the vertical clock signal C2 and the compensation clock signal CX2 that is output from the switch S2. The OR gate 37 ORs an output signal L1 of the LSB portion 33L of the horizontal counter 33 and a gate output signal E1 of the AND gate 35 and outputs the resultant signal to the least significant bit of an MSB portion 33M of the counter 33. The OR gate 38 ORs an output signal L2 of an LSB portion 34L of the vertical counter 34 and a gate output signal E2 of the AND gate 36 and outputs the resultant signal to the least significant bit of an MSB portion 34M of the counter 34.
Next, an operation of the above related art reference will be described.
First of all, picture data G from a CPU bus 4 is stored in the image memory 9. At this point, since a selector 40 has selected a CPU bus 4, the picture data G is stored corresponding to the storage address AG.
Thereafter, before the image memory 9 outputs picture data G', the compensation memory portions 11 and 12 of the compensation memory 10 store the horizontal magnification information X1 and the vertical magnification information X2 through the CPU bus 4, respectively. At this point, since the selectors 25 and 26 have selected the CPU bus 4, the magnification information X1 and X2 are stored corresponding to the storage addresses AX1 and AX2, respectively.
When the picture data G is magnified to 4/3 times the picture data G in both the horizontal direction and the vertical direction, a flag of the multiplication information X that represents the enlargement is set to "1". In addition, "1" is written to addresses 4n (where n=0, 1, 2, . . . and so forth) and "0" is written to addresses 4n+1, 4n+2, and 4n+3 so that data corresponding to each repetitive line of the picture data G becomes "1" and data corresponding to each non-repetitive line of the picture data G becomes "0".
When the picture data G' is read from the image memory 9, the selector 40 selects the counter circuit 30. The selectors 25 and 26 select the counters 23 and 24, respectively. Thus, in synchronization with the clock signal C that is a picture data transmission timing signal, the compensation clock signal CX is read from the compensation memory 10 corresponding to the multiplication information X. Therefore, the compensation clock signals CX1 and CX2 respectively are inputted to the counter circuit 30.
Since the flag that represents the enlargement has been set to "1", the switches S1 and S2 are opened. The AND gates 35 and 36 prohibit signals from flowing. On the other hand, the compensation clock signals CX1 and CX2 inverted by the inverters IN1 and IN2 are output to the AND gates 31 and 32, respectively. Thus, when the logic level of the compensation clock signal CX is "1", the logic level the gate output signal D becomes "0". Thus, a pulse-shaped gate output signal D of which the clock signals C1 and C2 corresponding to the addresses 4n have been thinned out is obtained (see a time chart shown in FIG. 3B).
The gate output signals D1 and D2 are output to the LSB portion 33L of the horizontal counter 33 and the LSB portion 34L of the vertical counter 34, respectively. Thus, the compensation address AC (see FIG. 3B) of which an address corresponding to 3G is repeated is output.
The picture data G stored in the image memory 9 is read in such a manner that the same line is repeatedly read on every fourth occasion. Thus, the picture data G' is magnified 4/3 times to the picture data G.
In the above-described conventional horizontal magnifying circuit for 4 : 2 : 2 or 4 : 1 : 1 video signals, when clock signals are thinned out corresponding to the flag representing the enlargement, since odd number data and even number data of color difference signals share the bus, it is not assured whether or not a thin-out signal becomes active when odd number data or even number data of the color difference signals is input. Thus, while the odd number data of the color difference signals is being input, when the thin-out signal becomes active, the video data width of odd number data does not accord with the video data width of even number data. Consequently, colors of the resultant picture data become unnatural.
FIG. 4 shows a time chart of the related art reference as shown in FIG. 3. In FIG. 4, when an NTSC video signal (luminance data) 401 and an NTSC video signal (color difference signal) 402 are read from the image memory 9 corresponding to the thin-out signal 404, and when the thin-out signal 404 is input while odd number data of the color difference data being input after the start signal 403, the video data width of CR1 does not accord with the video data width of CB1 for the Y (luminance) signal 405, the CR signal (color difference signal) 406, and the CB signal (color difference signal) 407. Thus, the colors of the resultant picture data become unnatural.